1. Field of the Invention
The present disclosure generally relates to the field of fabricating semiconductor devices, and, more particularly, to metallization systems including low-k dielectric materials.
2. Description of the Related Art
Today's global market forces manufacturers of mass products to offer high quality products at a low price. It is thus important to improve yield and process efficiency to minimize production costs. This holds especially true in the field of semiconductor fabrication, since here it is essential to combine cutting-edge technology with volume production techniques. One important aspect in realizing the above strategy is seen in continuously improving device quality with respect to performance and reliability, while also enhancing the diversity of functions of semiconductor devices. These advances are typically associated with a reduction of the dimensions of the individual circuit elements, such as transistors and the like. Due to the continuous shrinkage of critical feature sizes, at least in some stages of the overall manufacturing process, frequently new materials may have to be introduced to adapt device characteristics to the reduced feature sizes. One prominent example in this respect is the fabrication of sophisticated metallization systems of semiconductor devices in which advanced metal materials, such as copper, copper alloys and the like, are used in combination with low-k dielectric materials, which are to be understood as dielectric materials having a dielectric constant of approximately 3.0 and significantly less, in which case these materials may also be referred to as ultra low-k (ULK) dielectrics. By using highly conductive metals, such as copper, the reduced cross-sectional area of metal lines and vias may at least be partially compensated for by the increased conductivity of copper compared to, for instance, aluminum, which has been the metal of choice over the last decades, even for sophisticated integrated devices.
On the other hand, the introduction of copper into semiconductor manufacturing strategies may be associated with a plurality of problems, such as sensitivity of exposed copper surfaces with respect to reactive components, such as oxygen, fluorine and the like, the increased diffusion activity of copper in a plurality of materials typically used in semiconductor devices, such as silicon, silicon dioxide, a plurality of low-k dielectric materials and the like, copper's characteristic of generating substantially no volatile byproducts on the basis of typically used plasma enhanced etch processes, and the like. For these reasons, sophisticated inlaid or damascene process techniques have been developed in which typically the dielectric material may have to be patterned first in order to create trenches and via openings, which may then be coated by an appropriate barrier material followed by the deposition of the copper material. Consequently, a plurality of highly complex processes, such as the deposition of sophisticated material stacks for forming the interlayer dielectric material including low-k dielectrics, patterning the dielectric material, providing appropriate barrier and seed materials, filling in the copper material, removing any excess material and the like, may be required for forming sophisticated metallization systems, wherein the mutual interactions of these processes may be difficult to assess, in particular as material compositions and process strategies may frequently change in view of further enhancing overall performance of the semiconductor devices.
For example, the continuous shrinkage of the critical dimensions may also require reduced dimensions of metal lines and vias formed in the metallization system of sophisticated semiconductor devices which may lead to closely spaced metal lines, which in turn may result in increased RC (resistive capacitive) time constants. These parasitic RC time constants may result in significant signal propagation delay, thereby limiting overall performance of the semiconductor device, although highly scaled transistor elements may be used in the device level. For this reason, the parasitic RC time constants may be reduced by using highly conductive metals, such as copper, in combination with dielectric materials of very reduced permittivity, also referred to as ULK materials, as previously discussed. On the other hand, these materials may exhibit significant reduced mechanical and chemical stability, for instance when exposed to the various reactive etch atmospheres, for instance during etch processes, resist removal and the like, thereby increasingly creating a damage zone at the exposed surface portions of these sensitive dielectric materials. The damaged surface portions, however, may result in reduced reliability of the overall metallization system, that is, a premature device failure may occur during operation of the device and/or subsequent process steps may be significantly affected by the damaged surface portions, thereby also contributing to a reduced overall performance and reliability. For these reasons, the damaged surface portions may be removed prior to subsequent process steps, which may also be associated with certain negative effects on the finally obtained semiconductor device, as will be described in more detail with reference to FIGS. 1a-1b. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 at a manufacturing stage in which a metallization system is to be formed on the basis of sensitive dielectric materials in combination with highly conductive metals. As illustrated, the semiconductor device 100 comprises a substrate 101 above which may be formed a plurality of device levels, i.e., various levels in which circuit elements and other device features may be formed. For example, the substrate 101 may have incorporated therein an appropriate semiconductor layer in and above which circuit elements, such as transistors and the like, may be formed in accordance with design rules. Furthermore, any appropriate contact structures connecting to the circuit elements may be provided which for convenience are not shown in FIG. 1a. Furthermore, a metallization system 120 may comprise a plurality of metallization layers of which a metallization layer 110 and an adjacent metallization layer 130 are illustrated in FIG. 1a. For example, the metallization layer 110 may comprise any appropriate dielectric material 111, such as a low-k dielectric material, the dielectric constant of which may be 3.0 or significantly less, when the ULK material is used. It should also be appreciated that the dielectric material 111 may comprise different material compositions, depending on the overall device requirements. Furthermore, a plurality of metal lines 112 may be formed in the dielectric material 111 and may represent respective metal lines or any other metal regions as are required according to the overall circuit layout of the device 100. The metal lines 112 may comprise a conductive barrier material 112A, which may act as an interface between a highly conductive metal 112B, such as copper, copper alloy and the like, and the dielectric material 111. Thus the conductive barrier material 112A may suppress any diffusion of reactive components, such as oxygen, fluorine and the like, to the copper-based metal 112B in order to suppress any unwanted chemical reaction, while on the other hand out-diffusion of copper atoms into the surrounding dielectric material 111 may also be suppressed by the barrier material 112A. For example, tantalum nitride, tantalum and the like are well-established barrier materials used to provide the desired chemical and mechanical integrity of the copper-based metal 112B.
Furthermore, dielectric layers 113 and 114 may be formed above the dielectric material 111 to act as an interface for providing the required chemical and mechanical characteristics. For example, the layer 113 may act as an efficient etch stop layer and may also provide a desired confinement of the metal 112B in the metal lines 112. For example, silicon nitride may frequently be used wherein, however, in highly advanced applications, a moderately high dielectric constant of silicon nitride materials may be considered as inappropriate and therefore silicon carbide-based materials may be used or any other dielectric materials providing a reduced dielectric constant while nevertheless having the desired characteristics with respect to metal confinement and/or etch stop capabilities may be used. Similarly, the layer 114 may act as an appropriate base material so as to form thereon a sensitive low-k dielectric material, such as a ULK material 131 of the metallization layer 130. Furthermore, the metallization layer 130 may comprise a plurality of openings in accordance with the overall device requirements. For example, trench openings 131T may be formed in an upper portion of the dielectric material 131, while a via opening 131V may be provided to connect the trenches 131T to one of the metal lines 112 in the metallization layer 110 at any appropriate position. As previously explained, in particular, the via openings 131V may have to be formed in accordance with tightly set process tolerances and may typically represent the features having the critical dimensions of the corresponding metallization level, since the via openings 131V may have to be aligned to the metal lines 112, which may also be formed on the basis of tightly set lateral dimensions.
Typically, the semiconductor device 100 may be formed on the basis of wellestablished process techniques which may include the formation of any circuit elements in the device level (not shown) followed by an appropriate manufacturing sequence for providing a contact structure. Thereafter, the metallization system 120 may be formed by depositing an appropriate dielectric material, such as the layers 113, 114, depending on the material characteristics of the lower lying device level. It should be appreciated that the metallization layer 110 may be formed in accordance with substantially the same process techniques as will be described with respect to the metallization layer 130. Hence, a respective explanation will be omitted here. Thus, after forming the metallization layer 110, the dielectric material 131 may be deposited, for instance in the form of a silicon-containing material, which may exhibit the desired low dielectric constant, as previously explained. For this purpose, a plurality of well-established chemical vapor deposition (CVD) techniques are available. Thereafter, a complex patterning sequence may be performed, for instance including the deposition of any anti-reflective coating (ARC) materials in combination with resist materials to provide an appropriate etch mask, for instance, for first defining the via openings 131V. The corresponding patterning sequence may represent a critical process sequence, since the lithography as well as the subsequent etch patterning strategies may be designed to provide the smallest feature sizes that may consistently be achieved so that any further reduction of the lateral dimensions, for instance of the via opening 131V, may not be compatible with the corresponding manufacturing sequence. Thus, the via opening 131V may be formed on the basis of a corresponding lithographically defined etch mask, which may subsequently be removed and a corresponding further etch mask may be formed by lithography to define the position and lateral size of the trench openings 131T. In a subsequent etch process, the trench openings 131T may be formed in the upper portion of the dielectric material 131, while also the via opening 131V may be opened so as to extend to the corresponding metal lines 112. Thereafter, any resist material may be removed and the finally obtained surface may be subjected to appropriate cleaning processes, depending on the overall process strategy. As previously explained, during the preceding complex patterning process, the material 131 is exposed to reactive atmospheres, which may result in a certain degree of damage, thereby creating a damaged surface layer 132, which may also be present on inner surface areas of the trench openings 131T and the via openings 131V. Due to the significantly different material characteristics of the damaged surface layer 132, severe reliability problems may occur during the further processing and the operation of the device 100. Consequently, the damaged surface layer 132 may be removed by an appropriate etch recipe, which may typically be based on any appropriate acids or other agents, such as HCl and the like.
FIG. 1b schematically illustrates the semiconductor device 100 during a corresponding isotropic etch process 102, for instance on the basis of HCl, in order to remove the layer 132. Depending on the overall process strategy, a thickness of the layer 132 may range from 1-10 nm, and hence the process parameters, such as etch time and the like, during the process 102 may be selected so as to substantially completely remove the layer 132, even if the thickness of the layer 132 may vary depending on the overall device topography. Consequently, the dimensions of the openings 131T, 131V may be increased according to the thickness of the layer 132 and the parameters of the etch process 102, thereby resulting in an increase of the corresponding “critical” dimensions. Consequently, the further processing may have to be performed on the basis of increased critical dimensions, since a corresponding increase may not be taken into consideration when applying the corresponding patterning sequence for forming the openings 131T, 131V, due to the limitations with respect to lithography and associated etch techniques. Consequently, the increase of the critical dimensions may have to be taken into consideration in the basic device design of the device 100, which may result in a less pronounced performance gain when continuously shrinking critical dimensions of semiconductor devices. On the other hand, continuing the processing of the device 100 on the basis of the minimum critical dimensions, i.e., without removing the damaged layer 132, may result in an unacceptable increase of yield losses.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.